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 Integrated Circuit Systems, Inc.
ICS9248-179
Preliminary Product Preview
Frequency Generator for Intel Pentium III Celeron Processor
Recommended Application: Single chip clock solution for SIS 635/640 Intel Pentium III Celeron chipset. Output Features: * 2 - CPUs @ 2.5V. * 1 - IOAPIC @ 2.5V. * 1 - SDRAM @ 3.3V * 6- PCI @3.3V * 2 - AGP @ 3.3V * 1- 48MHz, @3.3V fixed. * 1- 24/48MHz, @3.3V selectable by I2C (Default is 24MHz) * 2- REF @3.3V, 14.318MHz. Features: * Up to 166MHz frequency support * Support FS0-FS3 trapping status bit for I2C read back. * Support power management: CPU, PCI, SDRAM stop and Power down Mode from I2C programming. * Spread spectrum for EMI control (0 to -0.5%, 0.25%). * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: < 175ps * PCI - PCI: < 500ps * CPU - SDRAM: < 250ps * CPU (early) - PCI: 1-4ns (typ. 2ns) * AGP - AGP: <175ps * CPU - AGP: 1-4ns
Pin Configuration
*FS1/REF1 GND GND X1 X2 GND 2 FS2/PCICLK_F 2 FS3/PCICLK0 VDDPCI 2 **FS4/PCICLK1 **PCICLK2 GND **PCICLK3 **PCICLK4 VDDAGP AGPCLK0 AGPCLK1 GND VDD48 48MHz 2 1 AGPSEL/ 24_48MHz GND
2 *FS0/REF0 2
VDDREF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDLAPIC IOAPIC* GND VDDL CPUCLK0 NC GND VDDL CPUCLK1 GND NC NC VDDSDR SDRAM GND 2 PCI_STOP# 2 CPU_STOP# 1 PD# 2 SDRAM_STOP# 2 AGP_STOP# SDATA SCLK GND VDD
48-Pin 300mil SSOP
* These are double strength. ** (1X/2X) have single or double strength to drive 2 loads. 1. Internal pull-up, of 120K to VDD. 2. These inputs have a 120K pull down to GND.
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz
Functionality
FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 66.66 100 166.66 133.33 66.66 100 100 133.33 112 124 138 150 66.66 133.33 150 160 SDRAM PCICLK 66.66 100 166.66 133.33 100 66.66 133.33 100 112 124 138 150 133.33 166.66 100 120 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.6 31 34.5 30 33.33 33.33 30 30 AGP SEL AGP SEL =0 =1 66.66 50 66.66 50 66.66 55.6 66.66 50 66.66 50 66.66 50 66.66 50 66.66 50 67.2 56 62 46.5 69 46.0 60 50 66.66 49.84 66.66 55.3 60 50 60 48
2
REF (1:0)
CPU DIVDER
Stop
2
CPUCLK (1:0)
IOAPIC DIVDER
Stop
IOAPIC SDRAM
SDATA SCLK FS (4:0) PD# PCI_STOP# CPU_STOP# SDRAM_STOP# AGP_STOP# AGP_SEL
Control Logic
SDRAM DIVDER
Stop
PCI DIVDER
Stop
5
PCICLK (4:0) PCICLK_F
Config. Reg.
AGP DIVDER
2
AGP (1:0)
Note: Please see full table on page 4.
9248-179 Rev B 08/22/01 Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9248-179
ICS9248-179
Preliminary Product Preview
Pin Configuration
PIN NUMBER 1, 11, 17, 21, 25, 36 2 3 4, 5, 8, 14, 20, 24, 26, 34, 39, 42, 46 6 7 9 10 12 16, 15, 13 19, 18 22 23 27 28 29 30 PIN NAME VDD FS0 REF0 FS1 REF1 GND X1 X2 FS2 PCICLK_F FS3 PCICLK0 FS4 PCICLK1 PCICLK (4:2) AGPCLK (1:0) 48MHz AGPSEL 24_48M Hz SCLK SDATA AGP_STOP# SDRAM_STOP# TYPE PWR IN OUT IN OUT PWR IN OUT IN OUT IN OUT IN OUT OUT OUT OUT IN OUT IN I/O IN IN DESCRIPTION 3.3V Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48MHz output. Frequency select pin. 14.318 MHz reference clock. Frequency select pin. 14.318 MHz reference clock. Ground pin for outputs. Crystal input,nominally 14.318M Hz. Crystal output, nominally 14.318MHz. Frequency select pin. PCI clock output, not affected by PCI_STOP#. Frequency select pin. PCI clock output. Frequency select pin. PCI clock output. PCI clock outputs. AGP outputs defined as 2X PCI. These may not be stopped. 48M Hz output clock. AGP frequency select pin. Clock output for super I/O/USB default is 24M Hz. Clock pin of I C circuitry 5V tolerant. Data pin for I C circuitry 5V tolerant. Stops all AGP clocks besides the AGP_F clocks at logic 0 level, when input low. Stops all SDRAM clocks at logic 0 level, when input low. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Stops all CPUCLKs clocks at logic 0 level, when input low Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. SDRAM clock output. No connect pins. CPU clock outputs. Supply for CPU and IOAPIC clocks at 2.5V nominal.
2 2
31
PD#
IN
32 33 35 37, 38, 43 40, 44 41, 45, 48
CPU_STOP# PCI_STOP# SDRAM NC CPUCLK (1:0) VDDL
IN IN OUT OUT PWR
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2
ICS9248-179
Preliminary Product Preview
General Description
The ICS9248-179 is the single chip clock solution for Desktop/Notebook designs using the SIS 635/640 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-179 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDDCPU = CPU VDDPCI = PCICLK_F, PCICLK VDDSDR = SDRAM VDD48 = 48MHz, 24MHz, fixed PLL VDDA = Core, PLL, X1, X2 VDDAGP=AGP, REF
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3
ICS9248-179
Preliminary Product Preview
Serial Configuration Command Bitmap
Bytes 0-3: Are reserved for external clock buffer. Byte4: Functionality and Frequency Select Register (default = 0)
Description Bit 2 Bit 7 Bit 6 Bit 5 Bit 4 AGP CPU SDRAM PCI SEL = 0 FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 66.66 66.66 33.33 66.66 0 0 0 0 1 100 100 33.33 66.66 0 0 0 1 0 166.66 166.66 33.33 66.66 0 0 0 1 1 133.33 133.33 33.33 66.66 0 0 1 0 0 66.66 100 33.33 66.66 0 0 1 0 1 10 0 66.66 33.33 66.66 0 0 1 1 0 10 0 133.33 33.33 66.66 0 0 1 1 1 133.33 100 33.33 66.66 0 1 0 0 0 112 112 33.6 67.2 0 1 0 0 1 124 124 31 62 0 1 0 1 0 1 38 138 34.5 69 0 1 0 1 1 150 150 30 60 0 1 1 0 0 66.66 133.33 33.33 66.66 0 1 1 0 1 133.33 166.66 33.33 66.66 0 1 1 1 0 150 100 30 60 Bit 2 Bit 7:4 0 1 1 1 1 160 120 30 60 1 0 0 0 0 90 90 30 60 1 0 0 0 1 100.9 100.9 33.63 67.27 1 0 0 1 0 103 103 34.33 68.67 1 0 0 1 1 133.9 133.9 33.48 68.67 1 0 1 0 0 137.33 103 34.33 66.95 1 0 1 0 1 137.33 137.33 34.33 68.67 1 0 1 1 0 100.9 133.9 33.48 66.95 1 0 1 1 1 133.9 100.9 33.48 66.95 1 1 0 0 0 107 107 35.66 71.33 1 1 0 0 1 107 142.66 35.66 71.33 1 1 0 1 0 142.66 142.66 35.66 71.33 1 1 0 1 1 110 110 36.66 73.33 1 1 1 0 0 110 146.66 36.66 73.33 1 1 1 0 1 146.66 146.66 36.66 73.33 1 1 1 1 0 166.7 125 31.25 66.68 1 1 1 1 1 200.0 200.0 33.33 66.66 Bit 3 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit , 2 7:4 0 - No a Bit 1 1 - Sprrmd lSpectrum Enabled ea 0 - Running Bit 0 1- Tristate all outputs Bit PWD AGP SEL = 1 50 50 55.6 50 50 50 50 50 56 46.5 46.0 50 49.84 55.3 50 48 45 50.45 51.5 51.56 51.45 50.21 50.21 50.21 53.5 53.5 53.5 55 55 55 55.57 50 Spread Precentage 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread
00000 Note1
0 1 0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
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4
ICS9248-179
Preliminary Product Preview
Byte 5: CPU, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 23 2,3 47 3 2 23 22 PWD DESCRIPTION 1 24M_48M (1: On, 0: Off) REF_1X2X_Control 0 (0: 1x, 1: 2x) APIC1X2X_Control 1 (0: 1x, 1: 2x) 1 REF1 (Act/Inactive) 1 REF0 (Act/Inactive) IOAPIC Select 0 (0:16.67 MHz, 1:33.33 MHz) 24M_48M Select 1 (1: 24 MHz, 0: 48 MHz) 1 48MHz (Act/Inactive)
Byte 6: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 19 18 16 15 13 12 10 23
PWD 1 1 1 1 1 1 1 X
DESCRIPTION AGPCLK1 (Act/Inactive) AGPCLK0 (Act/Inactive) PCICLK4 (Act/Inactive) PCICLK3 (Act/Inactive) PCICLK2 (Act/Inactive) PCICLK1 (Act/Inactive) PCICLK0 (Act/Inactive) AGPSEL (read back)
Byte 7: Control, Active/Inactive Register (1= enable, 0 = disable)
Byte 8: Vendor ID Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit Bit Bit Bit 5 4 3 2
PIN# 12 13 10 9 3 2 15 16
PWD 0 0 X X X X X X
Bit 1 Bit 0
DESCRIPTION PCLCLK1_1X2X_Control (1: 2x, 0: 1x) PCLCLK2_1X2X_Control (1: 2x, 0: 1x) FS3 (read back) FS2 (read back) FS1 (read back) FS0 (read back) PCLCLK3_1X2X_Control (1: 2x, 0: 1x) PCLCLK4_1X2X_Control (1: 2x, 0: 1x)
BIT PIN# PWD Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 1
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
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5
ICS9248-179
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T A = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAM ETER Input High Voltage Input Low Voltage Supply Current Input frequency Input Capacitance 1 Transition Time 1 Settling Time Skew Skew 1
1 1 1
SYM BOL VIH VIL IDD IDDL Fi C IN C INX T tran s Ts T STAB
CONDITIONS
M IN 2 VSS -0.3
TYP
C L = 0 pF; Select @ 66M VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. 1.0 1.0
27
M AX UNITS VDD+0.3 V 0.8 V 180 mA 30 mA M Hz 5 pF 45 pF 3 3 4.0 4.0 ms ms ms ms ns
Clk Stabilization 1
T CPU-PCI VT = 1.5 V; VTL = 1.25V T CPU-SPREAD VT = 1.5 V; VTL = 1.25V
Guarenteed by design, not 100% tested in production.
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6
ICS9248-179
Preliminary Product Preview
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output Low Current Rise Time Fall Time
1 1
SYMBOL ZO VOH2B VOL2B IOL2B tr2B tf2B VDIF VDIF VX dt2B tsk2B tjcyc-cyc2B tjabs2B
CONDITIONS VO = VX Termination to Vpull-up(external) Termination to Vpull-up(external) VOL = 0.3 V VOL = 0.3 V, VOH = 1.2 V VOH = 1.2 V, VOL = 0.3 V Note 2 Note 2 Note 3 VT = 50% VT = 50% VT = VX VT = 50%
MIN
TYP
MAX
UNITS V V mA
1
1.2 0.4
18 0.9 0.9 0.4 0.2 550 45 Vpullup(external) + 0.6 Vpullup(external) + 0.6 1100 55 200 250 +250
ns ns V V mV % ps ps ps
Differential voltage-AC1 Differential voltage-DC1 Differential Crossover Voltage1 Duty Cycle1 Skew1 Jitter, Cycle-to-cycle1 Jitter, Absolute1
-250
Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 3 - Vpullup(external) = 1.5V, Min = Vpullup (external)/2-150mV; Max=(Vpullup (external)/2)+150mV
Electrical Characteristics - 24M , 48M , REF, AGP
T A = 0 - 70C; V DD = VDDL = 3.3 V +/-5%; C L = 20 pF (unless otherwise stated) PARAM ETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time Duty Cycle Jitter
1
SYM BOL RDSP 5
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -14 mA IOL = 6.0 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
M IN 20 20 2.4
TYP
M AX 60 60 0.4 -20
UNITS V V mA mA ns ns % ps
RDSN5 VOH5 VOL5 IOH5 IOL5 tr5 tf5
1 1 1 1
10 4.0 4.0 45.0 55.0 500
dt5
tj1s5
Guarenteed by design, not 100% tested in production.
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7
ICS9248-179
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP1 1 VO = VDD*(0.5) Output Impedance RDSN1 IOH = -18 mA Output High Voltage VOH1 Output Low Voltage VOL1 IOL = 9.4 mA VOH = 2.0 V Output High Current IOH1 Output Low Current IOL1 VOL = 0.8 V 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 VT = 1.5 V Duty Cycle dt1 1 VT = 1.5 V Skew Window tsk1 1 tj1s1 VT = 1.5 V Jitter
1
MIN 12 12 2.4
TYP
25
45.0
MAX UNITS 55 55 V 0.4 V -22 mA mA 2.0 ns 2.0 ns 55.0 % 500 ps 250 ps
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD =VDDL 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP2A VO = VDD*(0.5) 1 Output Impedance RDSN2A VO = VDD*(0.5) Output High Voltage VOH2A IOH = -28 mA Output Low Voltage VOL2A IOL = 19 mA Output High Current IOH2A VOH = 2.0 V Output Low Current IOL2A VOL = 0.8 V 1 Rise Time tr2A VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf2A VOH = 2.4 V, VOL = 0.4 V 1 Duty Cycle dt2A VT = 1.5 V 1 Jitter tcyc-cyc VT = 1.5 V
1
MIN 10 10 2.4
TYP
33 0.5 0.5 45
MAX UNITS 20 20 V 0.4 V -42 mA mA 2.0 ns 2 ns 55 % 250.0 ps
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-179
Preliminary Product Preview General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
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9
ICS9248-179
Preliminary Product Preview
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248179 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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10
ICS9248-179
Preliminary Product Preview
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-179. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-179. 3. All other clocks continue to run undisturbed. (including SDRAM outputs).
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11
ICS9248-179
Preliminary Product Preview
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-179. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-179 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-179 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248-179. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
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12
ICS9248-179
Preliminary Product Preview
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-179. All other clocks will continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
Notes: 1. All timing is referenced to the internal CPU clock. 2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to the SDRAM clocks inside the ICS9248-179. 3. All other clocks continue to run undisturbed.
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13
ICS9248-179
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT CPUCLKC
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-179 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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14
ICS9248-179
Preliminary Product Preview
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343 .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 48
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 15.748 MAX 16.002 MIN .620
D (inch) MAX .630
6/1/00 REV B
JEDEC MO-118 DOC# 10-0034
Ordering Information
ICS9248yF-179-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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15
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.


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